The present invention relates, in general, to testing of digital circuits, and more particularly to generation of test patterns to detect bridging faults in digital circuits.
According to the prior art, three approaches are typically taken concerning the problem of bridging faults in VLSI circuits. The first approach is to ignore the bridging faults. The problem with such an approach is that bridging faults have been shown to be the most common type of failure in some technologies. In addition, as stuck-at test pattern generators become more efficient and as test vector compacting schemes reduce the number of patterns applied to the silicon the expected fault coverage of bridging faults decreases. The second approach taken for detecting bridging faults has been to use wired logic to model the failures. Such an approach involves using either wired-OR, or wired-AND, or both to model the bridging faults that can occur in the circuit. This modeling is appropriate for some technologies: shorts in ECL do behave like wired-ORs and shorts in NMOS do behave like wired-ANDs. However, in technologies such as CMOS, the wired logic model is not accurate.
The third approach, typically used for detecting bridging faults in CMOS circuits, uses a monitor on the power supply current. When shorted nodes are driven to opposite values a direct connection is present between the power and ground lines on the chip. A much larger current than the normal static current will be drawn by the chip. As a result, the only test generation requirement is to ensure that all of the nodes in the circuit are driven to opposite values at least once during the test. This method has four major drawbacks. The first is that current measurements take much more time than that required to apply a test vector and sample the outputs logically. Test equipment would have to be slowed down significantly so that the current monitors could function properly. The second drawback is that many CMOS VLSI chips do not implement pure CMOS, but may also contain circuits that dissipate static power thereby masking the fault. The third drawback is that transistors with large leakage currents may mask the effect of the bridging fault. Finally, even if the leakage currents are small, the total leakage current on a VLSI chip may be sufficient to mask the effect of a single bridging fault. As a result, these chips may have such a high normal static current that current monitoring would be impractical.
In addition, some way must be used to reduce the total nodes tested, since exhaustively testing every pair of nodes in a VLSI circuit would be uneconomically slow. According to the prior art, the physical routing of each metal line is traced to determine the nearest neighbor for each segment. Alternatively, capacitance values are calculated between adjacent and crossing lines. The lines that correspond to these capacitances are then identified as potential bridging faults. While accurate, these methods are extremely slow.
There is a need for a test pattern generator which will detect bridging faults in all technologies. The test pattern generator has to be able to function at the gate level since a lower-level simulation would be uneconomically slow. The test pattern generator must detect both faults which create a feedback loop and faults which create no feedback loop. The test patterns must not be order dependent. Finally there is a need for a method to rapidly extract nodes which could potentially short together to minimize the number of tests required.